1. Technical Field
The present invention relates to a method and a device for driving a bistable liquid crystal display panel, and more particularly, to a method and a device for driving a bistable nematic dot-matrix liquid crystal display panel.
2. Background Art
FIG. 1 is a general functional block diagram for controlling display of a bistable liquid crystal display panel 10. The bistable liquid crystal display panel 10 is driven by a driving device including a common driving section (COM-IC) 11 for driving common lines in the horizontal direction, a segment driving section (SEG-IC) 12 for driving segment lines in the vertical direction, a power supply circuit 13 for generating drive potentials (V0, V12, V34, V5, and VCX), and a control section (MPU) 14 for controlling the common driving section 11, the segment driving section 12, and the power supply circuit 13.
Signals and functions of the control section 14 for controlling the common driving section 11 and the segment driving section 12 are the same as those in a normal STN driver circuit. For the common driving section 11, there are prepared an initialization signal RESETX, C-data for determining scan timing, a writing clock CL, an alternating current signal FRCOM, and DispOffx for display erasing. For the segment driving section 12, there are prepared the initialization signal RESETX, S-data for providing display image data, a writing clock XCK, an alternating current signal FRSEG, and DispOffx for display erasing.
FIG. 2 is an explanatory diagram of switching between the states of bistable nematic liquid crystal, illustrating how to switch the twist direction of nematic liquid crystal molecules to two kinds of states, called twisted state (Twisted) and uniform state (Uniform), by applying specific signals to commons and segments of the bistable liquid crystal display panel 10.
Note that, in the drawings attached to this application, COM represents a common signal applied to a common electrode, COM-Scan represents a common signal at the time of selection, that is, a selection signal, COM-No Scan represents a common signal at the time of non-selection, that is, a non-selection signal, SEG represents a segment signal applied to a segment electrode, and COM-SEG represents a common-segment voltage, that is, a display voltage applied to an intersection pixel sandwiched by the common electrode and the segment electrode. Then, the above-mentioned write signal is divided into two kinds of signals, a white write signal and a black write signal, and the above-mentioned display signal is divided into two kinds of voltages, a white display voltage and a black display voltage.
In the beginning, the case of displaying white (White) at an intersection pixel between the common electrode and the segment electrode of the bistable liquid crystal display panel 10 is described. As illustrated in the uppermost stage on the left side of FIG. 2, the voltage waveform of the selection signal applied to the common terminal is a waveform which has the level of 0 for a first time interval “a” of a selection period T, a negative level −V for time intervals “b” and “c”, a positive level +V for subsequent time intervals “d” and “e”, a positive level +VCX(=+V−v) for a subsequent time interval “f”, and the level of 0 for a remaining time interval “g”.
As illustrated in the second stage on the left side of FIG. 2, the voltage waveform of the white write signal applied to the segment terminal is a waveform which has the level of 0 for the first time intervals “a” to “e” of the selection period T, a negative level −v for the subsequent time interval “f”, and the level of 0 for the remaining time interval “g”.
When such time-varying selection signal and time-varying white write signal as described above are applied, the waveform of the white display voltage, which is a voltage difference between the common terminal and the segment terminal, becomes a time-varying waveform. That is, as illustrated in the third stage on the left side of FIG. 2, the waveform of the white display voltage is a waveform which has the level of 0 for the first time interval “a” of the selection period T, the negative level −V for the subsequent time intervals “b” and “c”, the positive level +V for the subsequent time intervals “d” to “e”, and the level of 0 for the remaining time interval “g”. This way, the waveform of the white display voltage shows a voltage transition between the negative level −V volts and the positive level +V.
The reason why the white display voltage having such waveform as described above is applied to the nematic liquid crystal is as follows. First, a stable state of orientation of the nematic liquid crystal molecules is broken by the voltage having the negative level −V to raise the nematic liquid crystal molecules in the longitudinal direction (see the schematic diagram on the left in the lowermost stage on the left side of FIG. 2). After that, the voltage having the positive level +V is released to the voltage having the level of 0 to lay the nematic liquid crystal molecules in an alignment direction (see the schematic diagram on the right in the lowermost stage on the left side of FIG. 2), to thereby set the twisted state (Twisted). This way, the intersection pixel of the bistable liquid crystal display panel 10 applied with the white display voltage having the waveform illustrated in the third stage on the left side of FIG. 2 displays white.
Next, the case of displaying black at the intersection pixel between the common electrode and the segment electrode of the bistable liquid crystal display panel 10 is described. The voltage waveform of the selection signal applied to the common terminal is identical to the waveform illustrated in the uppermost stage on the left side of FIG. 2.
As illustrated in the second stage on the right side of FIG. 2, the voltage waveform of the black write signal is a waveform which has the level of 0 for the first time intervals “a” to “c” of the selection period T, the negative level −v for the subsequent time interval “d”, and the level of 0 for the remaining time intervals “e” to “g”.
When such time-varying selection signal and time-varying black write signal as described above are applied, the waveform of the black display voltage, which is a voltage difference between the common terminal and the segment terminal, becomes a time-varying waveform. That is, as illustrated in the third stage on the right side of FIG. 2, the waveform of the black display voltage is a waveform which has the level of 0 for the first time interval “a” of the selection period T, the negative level −V for the subsequent time intervals “b” and “c”, a positive level +(V+v) for the subsequent time interval “d”, the positive level +V for the subsequent time interval “e”, the positive level +VCX(=+V−v) for the subsequent time interval “f”, and the level of 0 for the remaining time interval “g”. This way, the black display voltage shows a voltage transition between −V and +(V+v).
The reason why the black display voltage having such waveform as described above is applied to the nematic liquid crystal is as follows. First, astable state of orientation of the nematic liquid crystal molecules is broken by the voltage having the negative level −V to raise the nematic liquid crystal molecules in the longitudinal direction (see the schematic diagram on the left in the lowermost stage on the right side of FIG. 2). After that, the positive level +(V+v) is sequentially reduced in stages so that the positive level +(V+v) is reduced to the positive level +V, the positive level +V is reduced to the positive level +VCX(=+V−v), and at the end, the positive level +VCX(=+V−v) is reduced to the level of 0 so as to align the nematic liquid crystal molecules in substantially parallel (see the schematic diagram on the right in the lowermost stage on the right side of FIG. 2), to thereby set the uniform state (Uniform). This way, the intersection pixel of the bistable liquid crystal display panel 10 applied with the black display voltage illustrated in the third stage on the right side of FIG. 2 displays black.
FIG. 3 illustrates exemplary voltage waveforms applied to the common terminals and the segment terminal of the bistable liquid crystal display panel 10. The left side of FIG. 3 schematically illustrates a part of the bistable liquid crystal display panel 10 including common terminals in three successive rows, that is, an n-th row common terminal COM[n], an (n+1)th row common terminal COM[n+1], and an (n+2)th row common terminal COM[n+2], and segment terminals in three columns intersecting the three rows, that is, an m-th segment terminal SEG[m], an (m+1)th segment terminal SEG[m+1], and an (m+2)th segment terminal SEG[m+2].
Further, the right side of FIG. 3 illustrates voltage waveforms with the passage of time applied to the common terminals COM[n], COM[n+1], and COM[n+2] in the three successive rows and to the m-th segment terminal SEG[m] intersecting the common terminals of the bistable liquid crystal display panel 10. Note that, portions encircled by the broken lines are voltage waveforms of selection signals.
A voltage waveform of the selection signal applied to each of the common terminals at the time of selection (Scan) is, as illustrated in each of the first stage to the third stage from the top on the right side of FIG. 3, a waveform which has the level of 0 for the first time interval “a” of the selection period T, a positive level +V3 for the subsequent time interval “b”, the level of 0 for subsequent time intervals “c” and “d”, a positive level +V2 for the subsequent time interval “e”, and the level of 0 for the time interval “f”. Note that, V3>V2.
A voltage waveform of a non-selection signal applied to each of the common terminals at the time of non-selection is, as illustrated in each of the first stage to the third stage from the top on the right side of FIG. 3, a waveform which has the level of 0 for the first time intervals “a” and “b” of the selection period T, the positive level +V3 for the subsequent time intervals “c” to “e”, and the level of 0 for the remaining time interval “f”.
The voltage waveform of the signal applied to the common terminal is significantly different between FIGS. 2 and 3. That is, the voltage waveform of the selection signal illustrated in FIG. 2 is a voltage waveform showing a significant change to the positive and negative, but the voltage waveform of the selection signal illustrated in FIG. 3 is a waveform showing a significant change to only the positive side. Note that, although the non-selection signal is not illustrated in FIG. 2, the non-selection signal illustrated in FIG. 3 also has a waveform showing a significant change to only the positive side.
As illustrated in the first stage from the top on the right side of FIG. 3, the n-th row common terminal COM[n] is applied with the selection signal for a scan time section t1 and the non-selection signals for scan time sections t2 and t3. As illustrated in the second stage from the top on the right side of FIG. 3, the subsequent (n+1)th row common terminal COM[n+1] is applied with the non-selection signal for the scan time section t1, the selection signal for the scan time section t2, and the non-selection signal for the scan time section t3. As illustrated in the third stage from the top on the right side of FIG. 3, the subsequent (n+2)th row common terminal COM[n+2] is applied with the non-selection signals for the scan time sections t1 and t2 and the selection signal for the scan time section t3.
A voltage waveform of a segment voltage applied to the segment terminal, that is, the white write signal and the black write signal, is illustrated in the fourth stage from the top on the right side of FIG. 3. In this case, the white write signal is applied for the scan time section t1, the black write signal is applied for the scan time section t2, and the white write signal is applied for the scan time section t3.
The voltage waveform of the white write signal is a waveform which has the level of 0 for the first time intervals “a” and “b” of the selection period T, the positive level +V3 for the subsequent time intervals “c” and “d”, a positive level +V4 for the subsequent time interval “e”, and the level of 0 for the remaining time interval “f”.
Further, the voltage waveform of the black write signal is a waveform which has the level of 0 for the first time intervals “a” and “b” of the selection period T, the positive level +V4 for the subsequent time interval “c”, the positive level +V3 for the subsequent time intervals “d” and “e”, and the level of 0 for the remaining time interval “f”.
When the selection signal or the non-selection signal is applied to the common terminals and the white write signal or the black write signal is applied to the segment terminal as described above, common-segment voltages between the common terminals and the segment terminal, that is, the white display voltage and the black display voltage, as illustrated in the first stage to the third stage from the bottom on the right side of FIG. 3, are obtained.
That is, as illustrated in the third stage from the bottom on the right side of FIG. 3, an intersection pixel between the n-th row common terminal COM[n] and the m-th segment terminal SEG[m] in the scan time section t1 is applied with a white display voltage of a waveform which has the level of 0 for the first time interval “a” of the selection period T, the positive level +V3 for the subsequent time interval “b”, a negative level −V3 for the subsequent time intervals “c” and “d”, a negative level −(V4−V2) for the subsequent time interval “e”, and the level of 0 for the remaining time interval “f”.
In the scan time section t2, the intersection pixel is applied with a first parasite signal of a voltage waveform which has the level of 0 for the first time intervals “a” and “b” of the selection period T, a negative level −V1 for the subsequent time interval “c”, and the level of 0 for the remaining time intervals “d” to “f”. Further, in the scan time section t3, the intersection pixel is applied with a second parasite signal of a voltage waveform which has the level of 0 for the first time intervals “a” to “d” of the selection period T, the negative level −V1 for the subsequent time interval “e”, and the level of 0 for the remaining time interval “f”.
Next, as illustrated in the second stage from the bottom on the right side of FIG. 3, an intersection pixel between the (n+1) th row common terminal COM[n+1] and the m-th segment terminal SEG[m] is applied with the second parasite signal in the scan time section t1, a black display voltage in the scan time section t2, and the first parasite signal in the scan time section t3. The black display voltage is a voltage of a waveform which has the level of 0 for the first time interval “a” of the selection period T, the positive level +V3 for the subsequent time interval “b”, the negative level −V4 for the subsequent time interval “c”, the negative level −V3 for the subsequent time interval “d”, a negative level −(V3−V2) for the subsequent time interval “e”, and the level of 0 for the remaining time interval “f”.
Further, as illustrated in the first stage from the bottom on the right side of FIG. 3, an intersection pixel between the (n+2)th row common terminal COM[n+2] and the m-th segment terminal SEG[m] is applied with the first parasite signal in the scan time section t1, the second parasite signal in the scan time section t2, and the white display voltage in the scan time section t3.
As described above, with regard to display on the bistable liquid crystal display panel 10, black/white for one line is determined by a signal state of one common which outputs a voltage waveform of a selection signal and signal states of all the segments, and by sequentially scanning all the commons for one frame, display for the whole screen is determined. Only one common of the whole screen is scanned at a moment, and the remaining majority of commons output a voltage waveform of a non-selection signal. When the amount of charges to be charged or discharged in the bistable liquid crystal display panel is considered, it is necessary to focus on a potential difference between the voltage of the non-selection signal, which is output by the majority of the commons, and the voltage of the white write signal or the black write signal applied to the segment terminals. Specifically, the parasite signal in the waveform of the common-segment voltage between the common terminal and the segment terminal greatly contributes to the amount of charges to be charged or discharged in driving the bistable liquid crystal display panel 10, and thereby affects the amount of current consumption.
FIG. 4 illustrates waveforms in a specific drive mode (Mode-C) of the bistable liquid crystal display panel 10. Four kinds of waveforms applied to the bistable liquid crystal display panel 10 are: the selection signal applied to the common terminal at the time of selection; the non-selection signal applied to the common terminal at the time of non-selection; the white write signal applied to the segment terminal; and the black write signal applied to the segment terminal. Their voltage waveforms are the same as those illustrated in FIG. 3.
FIG. 4 also illustrates four kinds of voltages applied to the intersection pixel between the common terminal and the segment terminal, that is, the white display voltage, the black display voltage, a first parasite signal 40, and a second parasite signal 40. Their voltage waveforms are the same as those illustrated in FIG. 3. Further, the actual voltage value and pulse width have temperature properties in which, as the temperature becomes low, the voltage rises and the pulse width becomes larger.
Numerals “1” and “0” illustrated on the lower side of FIG. 4 indicate control signals for the waveform of a common voltage applied to the common terminal and the waveform of a segment voltage applied to the segment terminal. The waveform of the common voltage is controlled based on four signals CCX, C-Data, FR, and DispOffx. The waveform of the segment voltage is controlled based on three signals S-Data, FR, and DispOffx. When a driver (not employing SA driving system) which is already commercially available and normally drives a general STN liquid crystal is used as a segment driving device, the output voltage is controlled by the three control signals based on an input/output table of a segment driver (SEG-Drv.) shown in FIG. 6. Hence, the correspondences between the segment control signals and the segment voltage waveforms illustrated in FIG. 4 are established.
The waveform of a common voltage for driving the bistable liquid crystal display panel 10 has the potential VCX, which does not appear during normal driving for the general STN liquid crystal, and hence a control signal for outputting the potential is expressed by CCX. When common output control is performed as shown in the column of the drive mode (Mode-C) in an input/output table of a common driver (COM-Drv.) shown in FIG. 7, the correspondences between the common control signals and the common voltage waveforms illustrated in FIG. 4 are established.
After the image is written into the bistable liquid crystal display panel 10 in the manner described above, even if the common voltage and the segment voltage are set to GND to put the bistable liquid crystal display panel 10 in a non-application state, the written display image is held. That is, even when power supply is turned off after image writing, the image on the bistable liquid crystal display panel 10 is displayed. Power is necessary for writing, but display after the writing can be performed with no power. This is the feature of the bistable liquid crystal display panel 10.
From the facts that the write waveform to the bistable liquid crystal display panel 10 contains a DC component as described above and that the liquid crystal molecules have not yet reached a stable state of anchoring force immediately after the end of writing but gradually become the stable state, it is considered that the charges still remain in liquid crystal even at the time point when the COM electrode and the SEG electrode have become GND.
The bistable liquid crystal display panel 10 has a structure in which liquid crystal is sandwiched by glass substrates, on each of which a transparent electrode, an insulating film, and an orientation film are formed in this order. The bistable liquid crystal display panel 10 has an equivalent circuit as illustrated in FIG. 5 when each film is regarded as a parallel circuit of a resistor and a capacitor. Further, a liquid crystal layer is also regarded as a parallel circuit of a resistor and a capacitor. In this case, the charges remaining in the liquid crystal layer after writing have two directions of discharge, that is, a direction of discharge to the transparent electrode side via the insulating film and the orientation film, and a direction of discharge by the resistance of the liquid crystal layer itself. However, the specific resistances of the insulating film, the orientation film, and the liquid crystal layer are so high that no current flows, and hence the charges remain for a relatively long time (several seconds to several minutes).
Further, when a positive DC voltage is applied to the COM electrode of the bistable liquid crystal display panel 10, the orientation film is broken in several hours even by about 1 V, and display cannot be performed. On the other hand, when a positive DC voltage is applied to the SEG electrode, ions are absorbed to the orientation film to change electrical characteristics. Therefore, although the residual charges resulting from single writing cause no problem because its period is short, the residual charges after writing break down the bistable liquid crystal display panel 10 as the number of rewriting increases.